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MP1018 flat panel monitor ccfl driver controller MP1018 rev 1.1_07/10/03 monolithic power systems, inc. 1 monolithic power systems general description the MP1018 is a cold cathode florescent lamp (ccfl) driver controller optimized for flat panel monitor applications. designed to run off 12 or 15v input supplies, the MP1018 can drive up to 30 lamps (150w) via four (4) external n channel mosfets. its full bridge architecture converts unregulated dc input voltages to the nearly pure sine waves required to ignite and operate ccf lamps. the MP1018 supports analog and burst dimming without the use of external components. it has soft on and off burst waveform shaping, lamp current regulation, transformer secondary current regulation, output over voltage protection and a dual mode fault timer. the MP1018 is available in the 28 lead tssop and soic packages. ordering information part number ? package temperature MP1018em tssop28 -20 to +85c MP1018ey soic28 -20 to +85c ev0019 MP1018 evaluation board * for tape & reel, use suffix ?z (MP1018em-z) features drives 4 external, low cost, n channel fets drives up to 30 lamps (150w) operates with 12v or 15v input supplies lamp current and voltage regulation analog and burst mode dimming control integrated burst mode oscillator and modulator burst mode, soft on and soft off open/short lamp protection output short circuit protection automatic recovery from esd event evaluation board available applications desktop lcd flat panel displays flat panel video displays lcd tvs and monitors figure 1: typical application circuit abrt en dbrt pwr gnd f1 c7 c15 c5 c4 c12 r5 c18 c16 r2 t1 r e f 1 1 0 1 1 2 0 n / c d r v r p g l m p 1 0 1 8 2 3 4 5 6 7 8 9 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 c o m p f t l v f b s c f b b y p a g n / c a b r t l g r p g r p r l b t l u g l o u t l d r v l l l g 2 5 2 6 2 7 2 8 2 3 2 1 2 4 2 2 o u t r l c f b u r g b o s c b t r d b r t e n p r r lamp4 c6 c3 c2 c1 l1 r6 c14 c10 c11 c13 c9 q1 q2 q3 q4 c17 c19 c20 lamp1 lamp2 lamp3 r1 r3 c8 r4
MP1018 flat panel monitor ccfl driver controller MP1018 rev 1.1_07/10/03 monolithic power systems, inc. 2 monolithic power systems absolute maximum ratings input voltage v prr, v prl 18.5v logic inputs -0.3v to 6.5v junction temperature 150 c power dissipation ( note 1 ) 1.2w junction temperature 150 c lead temperature (solder) 260 c operating frequency 150khz storage temperature ?55 c to +150 c recommended operating conditions input voltage v prr, v prl 8v to 17.5v analog brightness voltage v abrt 0v to 1.9v digital brightness voltage v dbrt 0v to 1.8v enable voltage v en 0v to 5.0v operating frequency 20khz to 100khz operating frequency (typical) 60khz operating temperature -20 c to + 85c thermal characteristics thermal resistance ja 105 c/w electrical specifications (unless otherwise specified v prr =v prl =17.5v, t a =25 c) parameters symbol condition min typ max units reference voltage output voltage v ref i ref =3ma 4.75 5.0 5.25 v reference current i ref 3.0 ma line regulation 8v < v prr =v prl < 17.5v 30 mv load regulation 0 < i ref < 3.0ma 30 mv supply current (note 1) supply current (disabled) v en =0v 10 ua supply current (enabled) 8v < v prr =v prl < 17.5v 1.6 2.5 ma shutdown logic fault timer threshold 1.1 1.2 1.3 v fault timer sink current v lvfb =5v, v scfb =0v 1 a fault timer source current open lamp v lvfb =0.1v, v scfb =0v 1 a secondary overload v scfb =1.4v 120 a enable input voltage low v (il) en 0.5 v enable input voltage high v (ih) en 2.0 v output drivers gate drive v g 6.3 v gate pull-down r gd note 2 0.5 ? gate pull-up r gu note 2 6.0 ? gate pull-up current i gu note 2 250 ma current limit threshold v ig note 2 1.3 v ton(min) v comp =0v, v prr =v prl =17.5v 500 ns ton(min) v comp =0v, v prr =v prl =8v 1500 ns
MP1018 flat panel monitor ccfl driver controller MP1018 rev 1.1_07/10/03 monolithic power systems, inc. 3 monolithic power systems electrical specifications (continued) (unless otherwise specified v prr =v prl =17.5v, t a =25 c) parameters symbol condition min typ max units brightness control sense full brightness v (il) v abrt = 2.0v 800 mv sense full dim v (il) v abrt = 0v 225 mv lamp current regulation 8v < v prr =v prl < 17.5v 2 5 % burst oscillator sink current i bosc 380 a burst oscillator peak voltage v bosc 1.7 1.8 1.9 v fault loop control open lamp threshold v (th) vlfb 0 v secondary current threshold v (th) csfb 1.2 v fault mode comp current i comp v vlfb <0v, v csfb >1.2v 450 a note 1: the input current is the sum of the current into prr and prl. note 2: this parameter is guaranteed by design. pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ref comp ft lvfb scfb agnd byp nc abrt nc lcfb bosc dbrt en pgl llg drvl outl ulg btl prl pgr lrg drvr outr urg btr prr
MP1018 flat panel monitor ccfl driver controller MP1018 rev 1.1_07/10/03 monolithic power systems, inc. 4 monolithic power systems table 1: pin designators pin no. pin name pin function 8,10 ------- not connected 1 ref internally regulated 5v reference voltage. by pass ref to ag with a 0.22f or greater capacitor. 2 comp regulation loop compensation node. connect a 2.2nf capacitor from comp to ag to compensate the lamp current regulation loop. 3 ft fault timing capacitor. connect a capacitor fr om ft to ag to set the fault timeout period. 4 lvfb lamp voltage regulation feedback input. use a capacitor divider from the lamp to ground. 5 scfb secondary current regulation feedback input. connect a current sense resistor from the transformer secondary low-side to pgnd to measure the secondary current. 6 agnd analog ground 7 byp bypass byp to ag with a 1nf capacitor. 9 abrt analog brightness control input. drive abrt with a 0v to 2v dc voltage to adjust the brightness between fully dim and fully bright. 11 lcfb lamp current regulation feedback input. lcfb measures the lamp current through a resistor from the lamp low-side connection to ground. 12 bosc burst-mode oscillator timing. place a capacitor from bosc to gnd and a resistor to ref to set the burst-mode frequency. 13 dbrt burst-mode (digital) brightness control input. the voltage at dbrt controls the burst-mode duty cycle. the voltage ranges from 0v to 1. 8v to set the duty cycle between dmin to 100% 14 en enable (on/off) input. drive en high to turn on the MP1018, dr ive it low to turn it off. 15 prr input power rail, right side. prr is the inpu t power for the right-side mosfet switches. connect prr to the input source at the dr ain of the right side high side mosfet. 16 btr bootstrap capacitor, right side. btr powers the right-side high-side mosfet gate driver. connect a 33nf capacitor from outr to btr. 17 urg high-side mosfet gate drive output, right si de. connect urg to the gate of the right- side, high-side mosfet. 18 outr bridge power output, right side. connect the source of the right-side, high-side mosfet, and the drain of the right-side, low-side mosfet to outr. 19 drvr 6v (internally generated) drive voltage rail, right side. drvr supplies power to the right- side mosfet drivers urg and lrg. bypass this pin with a 0.33 f capacitor. 20 lrg low-side mosfet gate drive output, right side. connect lrg to the right-side, low-side mosfet gate. lrg swings between pgr and drvr. 21 pgr power ground, right side. connect the source of the right-side mosfet to pgr. 22 prl input power rail, left side. prl is the inpu t power for the left-side mosfet switches. connect prl to the input source at t he drain of the left side high side mosfet. 23 btl bootstrap capacitor, left side. btr powers the left-side high-side mosfet gate driver. connect a 33nf capacitor from outl to btl. 24 ulg high-side mosfet gate drive output, left side. connect ulg to the gate of the left-side, high-side mosfet. 25 outl bridge power output, left side. connect the s ource of the left-side, high-side mosfet, and the drain of the left-side, low-side mosfet to outl. 26 drvl 6v (internally generated) drive voltage rail, left side. drvl supplies power to the left-side mosfet drivers ulg and llg. bypass this pin with a 0.33 f capacitor. 27 llg low-side mosfet gate drive output, left side. connect llg to the left-side, low-side mosfet gate. llg swings between pgl and drvl. 28 pgl power ground, left side. connect the source of the left-side mosfet to pgl.
MP1018 flat panel monitor ccfl driver controller MP1018 rev 1.1_07/10/03 monolithic power systems, inc. 5 monolithic power systems figure 2: functional block diagram internal regulators prr ref 5v + - + - 2.5v 75mv + - comp lcfb abrt scfb lvfb control logic & tsd dbrt bosc ft en q q s r q q s r q q t mux + - + - 1.2v + - drv 6vr drv 6vl btl urg out r out l llg l r g btr ulg drvr drvl ref prl pgl pgr feature description brightness control the MP1018 can operate in three modes: analog mode, burst mode with a dc input, or burst mode with an external pwm. the three modes are dependent on the pin connections as per table 1. choosing the required burst repetition frequency can be achieved by an rc combination, as defined in component selection. the MP1018 has a soft on and soft off feature to reduce noise, when using burst mode dimming. analog dimming and burst dimming are independent of each other and may be used together to obtain a wider dimming range. table 2: function mode function pin connection pin 9 pin 13 pin 12 abrt dbrt bosc analog mode 0 ? 1.9v v ref agnd burst mode with dc input voltage v ref 0 ? 1.8v r2 c8 burst mode from external source v ref pwm 1.5v brightness polarity : burst: 100% duty cycle is at 1.8v analog: 1.9v is maximum brightness
MP1018 flat panel monitor ccfl driver controller MP1018 rev 1.1_07/10/03 monolithic power systems, inc. 6 monolithic power systems feature description (continued) application information fault protection open lamp : the lvfb pin (#4) is used to detect whether an open lamp condition has occurred. during normal operation the vlfb pin is typically at 5v dc with an ac swing of +/- 2v. if an open lamp condition exists then the ac voltage on the vlfb line will swing below zero vo lts. when that occurs, the ic regulates the voltage to 10v p-p and a 1a current source will inject into the ft pin. if the voltage at the ft pin exceeds 1.2v, then the chip will shut down. excessive secondary current (shorted lamp) : the scfb pin (#5) is used to detect whether excessive secondary current has occurred. during normal operation the csfb voltage is a 1v p-p ac signal centered at zero volts d.c. if a fault condition occurs that increases t he secondary current, then the voltage at csfb will be greater than 1.2v. when that occurs, the ic regulates the csfb voltage to 2.4v p-p and a 120a current source will inject into the ft pin. if the voltage at the ft pin exceeds 1.2v, then the chip will shut down. fault timer : the timing for the fault timer will depend on the sourcing current, as described above, and the capacitor on the ft pin. the user can program the time for the voltage to rise before the chip detects a ?real? fault. when a fault is triggered, then the internal drive voltage (v drv ) will collapse from 6.2v to 0v. the reference voltage will stay high at 5.0v. if no fault is detected a 1 a current sink will re store ft to 0v. lamp startup the strike voltage of the lamp will always be guaranteed at any temperature because the MP1018 uses a resonant topology for switching the outputs. the device will continue to switch at the resonant frequency of the tank until the strike voltage is achieved. this eliminates the need for external ramp timing circuits to ensure startup. chip enable the chip has an on / off function, which is controlled by the en pin (#14). the enable signal goes directly to a schmitt trigger. the chip will turn on with an en = high and off with an en = low. pin 5 (scfb) : r4, c5 (secondary short protection) the r4 and c5 combination is used for feedback to the scfb pin to detect excessive secondary current. these components should have +/- 5% tolerance limits. the value for r4 is approximately 1k ? and c5 is approximately 330nf. this will ensure that the voltage at t he csfb pin is typically 1.0v during steady state operation. pin 4 (vlfb): c16, c4 and r1 (open lamp protection) the regulated open lamp voltage is proportional to the c16 and c4 ratio. c16 has to be rated at 3kv and is typically between 5 to 22pf. the value of c16 is typically 15pf and is chosen for a specified maximum frequency. the value of c4 is set by the customer to achieve the required open lamp voltage detection value, typically 4nf. c4=c16 * v(max)rms/ 3.5vrms) the value of r1 is typically 300k ? (not critical). pin 3 (ft): c3 the c3 cap is used to set the fault timer. this capacitor will determine when the chip will reach the fault threshold value. the user can choose the cap value to set the time out value. open lamp time c3 (nf) = t(open lamp) (1a)/ 1.2 v for a c3= 820nf, then the time out for open lamp will be 0.98 sec. secondary short turn off time because the sourcing current for a secondary short is approx. 120a, then the off time when a resistive short occurs across t he lamp will be approx 100 times faster than the open lamp time.
MP1018 flat panel monitor ccfl driver controller MP1018 rev 1.1_07/10/03 monolithic power systems, inc. 7 monolithic power systems application information (continued) to reduce the turn off time even further, then by modifying the connection at the ft node to: ft 10nf c3 100k figure 3: turn off time adjustment for a cap=10nf, then the time out for secondary short will be 0.11ms. the turn off time for the secondary short will be reduced by an additional 100 times. note: the open lamp time will remain the same value as defined by c3. pin 2 (comp): c2 this cap is the system compensation cap that connects between comp and agnd. a 1.5nf or 2.2nf cap is recommended. this cap should be x7r ceramic with a voltage rating sufficient for 5v biasing. the value of c2 affects the soft-on rise time and soft-off fall time. pin 15 (ref): c1 c1 is the bypass cap for t he internal 5.0v supply. this capacitor must be placed as close as possible to the pin. a maximum of 100 mils is recommended between the cap and the ic. the value of the cap is typically 0.47f pin 15 (prr), pin 18 (pgr), pin 21 (pgr), pin 22 (prl), pin 25 (outl), pin 28 (pgl) these pins are used to sense the voltages across the external power transistors. these voltages are used by the MP1018 to protect the power transistors in the event of an accidental short from the output of the bridge to ground or the positive rail. it also detects the zero crossings of the ac current in the primary of the power transformer. a secondary function of the prr and prl (positive rail right and left) is to power the internal bias regulators (ref, drvr and drvl). prr and prl should make a kelvin connection to the drains of the upper power transistors in the output bridge. pgr and pgl should make a kelvin connection to the sources of the lower transistors in the output bridge. outr and outl should make a kelvin connection to the sources of the upper transistors and the drains of the lower transistors in the output bridge. pin 13 (outl) & pin 8 (outr) : c15, r6, r5 the primary transformer current flows through this capacitor. its value is typically 1f and its voltage rating is sufficient for a 5v bias. the capacitor should be ceramic and have a ripple current rating greater than the primary curr ent (typically 2arms). it is more optimal to use two parallel 1f ceramic caps for minimal esr losses. r6 and r5 are used to ensure that the bridge outputs are at 0v prior to startup. typically r5 = 2.7k ? and r6 = 470 ? . pin 11 (btl) and pin 10 (btr): c10 and c12 these are the reservoir caps for the upper switches? gate drive. they should be 10nf and made of x7r ceramic material and have a voltage rating for 6.6v biasing. pin 6 (drv): c9 this bypasses the 6.2v gate supply for the lower switches. the value should be 100nf ceramic y5v or x7r material. pin 5: (en) this pin will enable and disable the chip. do not float this pin. pin 13 (dbrt) this pin is used for burst brightness control. the dc voltage on this pin will control the burst percentage on the output. the signal is filtered for optimal operation. the active range is approximately 0.1v to 1.8v. pin 12 (bosc): c8, r2 the c8 and r2 will set the burst repetition rate and the minimum burst time: t min. set t min to achieve the minimum required system brightness. ensure that t min is long enough that the lamp does not extinguish. these values are determined by the following . steps:
MP1018 flat panel monitor ccfl driver controller MP1018 rev 1.1_07/10/03 monolithic power systems, inc. 8 monolithic power systems application information (continued) 1) select a minimum duty cycle, d min , where: d min =t min * f bosc d min =t fall / (t fall + t rise ) 2) determine r2 by the formula: 1.68 * [(1 / d min ) ? 1] 0.42 3) select a burst frequency and then determine c8 by the formula: (1-d min ) 0.42 * r2 * f bosc where: f bosc = burst frequency rate in hz t min = minimum burst time in sec figure 4: burst oscillator wavefo rm versus output lamp current r2 = c8 = + 4 350 * 10 - 6
MP1018 flat panel monitor ccfl driver controller MP1018 rev 1.1_07/10/03 monolithic power systems, inc. 9 monolithic power systems figure 5: open lamp voltage setup and ul test protection application information
MP1018 flat panel monitor ccfl driver controller MP1018 rev 1.1_07/10/03 monolithic power systems, inc. 10 monolithic power systems package information tssop28 0.039(1.000)ref note: 1) control dimension is in inches. dimension in bracket is millimeters. 0.010(0.250) 0.018(0.450) 0.030(0.750) 0 o -8 o detail "a" gate plane 0.004(0.090) 0.004(0.090) see detail "a" see detail "b" 0.033(0.850) 0.047(1.200) 0.007(0.190) 0.012(0.300) 0.032(0.800) 0.041(1.050) 0.002(0.050) 0.006(0.150) 0.337 (9.600) 0.386 (9.800) seating plane 0.0256(0.650)typ pin 1 ident. 0.169 0.177 (4.300) (4.500) 0.244 0.260 (6.200) (6.600) 0.030(0.750) 0.030(0.750) 0.004(0.090) 0.008(0.200) 0.007(0.190) 0.010(0.250) 0.004(0.090) 0.006(0.160) 0.075(0.190) 0.012(0.300) detail "b"
MP1018 flat panel monitor ccfl driver controller MP1018 rev 1.1 monolithic power systems, inc. 11 07/10/03 983 university ave, building d, los gatos, ca 95032 usa ? 2003 mps, inc. tel: 408-395-2802 ? fax: 408-395-2812 ? web: www.monolithicpower.com monolithic power systems package information soic28 0.689 0.706 0.025 0.035 r = 0.026 ref 7bsc 0.020 0.040 0.050bsc 0.291 0.299 0.014 0.020 0.004 0.012 0.096 0.104 0.398 0.414 0.009 0.011 0 - 8 notice: mps believes the information in this document to be accu rate and reliable. however, it is subject to change without notice. please contact t he factory for current specifications. no respons ibility is assumed by mps for its use or fit to any application, nor for infringement of patent or other rights of third parties.

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